1. Field of the Invention
The present invention relates to a semiconductor integrated circuit, and in particular, to a semiconductor integrated circuit including a so-called clock tree.
2. Description of the Related Art
Logic circuits in semiconductor integrated circuits may have errors in their logic functionality due to the variations in delay time of clock signal. Thus, in order to provide uniformity in delay time of clock signal provided to circuits, clock tree cells are arranged on clock signal lines in a tree structure (hereinafter referred to as a “clock tree”), thereby accomplishing a uniform wiring (see Patent Document 1: Japanese Patent Laid-Open No. HEI 11-194848). However, while this method enables the variations in delay time to be reduced, some problems arise that the clock tree cells are sensitive to the voltage drop caused by the power consumption at other logic circuits, affecting the cycle of a clock signal to be driven (i.e., providing a larger clock skew). As development in current semiconductor integrated circuits is directed to further refinement, there also arise needs of corresponding increase in the frequency of clock signals, decrease in the power supply voltages, and increase in the size of circuit. These issues may exacerbate the problems described above.